View HT82V863R_7869825.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.00 1 september 30, 2011 rev. 0.00 pb september 30, 2011 HT82V863R ccd digital signal processor features ? input: supports y e, mg, cy, g colour flters for ntsc/pal, 270k/320k/410k/470k ccd sensors ? output: ntsc/pal analog cvbs ? automatic ccd defect compensation up to 50 bad pixels and 4 consequential bad pixels correction ? automatic back light compensation ? programmable false colour suppression ? programmable high light suppression ? programmable sharpness enhancement ? programmable colour saturation and hue function ? programmable contrast and brightness function ? programmable gamma curve ? integrate a 96-step ccd timing generator ? support ae/a wb algorithm function ? support osd function ? integrate a 2-d dnr function ? integrate the digital wdr ? integrate the digital line lock function to reduce colour rolling ? integrate a ntsc/pal video encoder ? integrate a 10-bit dac ? support ccir656 digital out ? integrate a one-channel 6-bit adc ? integrate otp rom with isp function for multiple programming codes ? support mirror function ? support a master i 2 c interface for external eeprom to store parameters ? support a slave i 2 c interface for communication with an external host ? embedded lvr and por circuits ? embedded 3.3v-to-1.8v regulator ? single 3.3v power supply ? 64/80-lqfp package general description the ht 82v863r i s a si ngle c hip di gital i mage processor for y e, cy , mg and g colour ccd video camera systems. it receives cf a patterns from colour ccds a nd ge nerates ntsc/ pal cvbs signa ls using internal video encoders and the 10-bit dac. in addition, it also provides an ae/a wb algorithm, timing generation module together w ith other circuitry. the device contains a microcontroller in which an otp ro m is integrated internally to implement the basic camera functions such as the ae/a wb algorithm. the video camera system consists of a cds/agc/adc ic (ht82v842a), dsp ic (HT82V863R), v ertical driver ic (ht82v805) and ccd sensors. it also provides a proprietary function to eli minate so call ed line cra wl and autom atic ccd defect compensation function to correct up to 30 bad pixels and 4 consequential bad pixels.
rev. 1.00 2 september 30, 2011 HT82V863R block diagram
rev. 1.00 3 september 30, 2011 HT82V863R pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 2021 2223 2425 26 2728 6061626364 29303132 5253545556575859 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 42 33 34 35 1718 19 495051 afe_din9 afe_din8 afe_din7 afe_din6 pvdd33 pvdd33 afe_din5 afe_din4 afe_din3 afe_din2 afe_din1 afe_din0 pvss afe_obp afe_pblk afe_adclp vref bias comp fsa avdd avss HT82V863R 64 lqfp-a pvddreg dvdd18 dvss pvss pvdd65 gpio1_sscl gpio2_ssda pvdd33 pclk_o pvss vd_v1 vd_v2 vd_v3 vd_v4 vd_vsg1 vd_vsg2 vd_vsub pvdd33 ccd_rg ccd_h1 ccd_h2 pvss afe_shp afe_shd video avdd op_inp op_out adc_in pvdd33 gpio6_ohs gpio5_pref pvss afe_ck afe_do gpio0_csn rst_n xout xin avss gpio3_mscl gpio4_msda 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 6463 62 61 60 59 58 57 56 55 54 53 52 51 40 49 48 afe_din9 ccir_d3 ccir_d2 ccir_d1 ccir_d0 pvss afe_din8 HT82V863R 80 lqfp-a afe_din7 afe_din6 pvdd33 pvdd33 afe_din5 afe_din4 afe_din3 afe_din2 afe_din1 afe_din0 afe_obp afe_pblk afe_adclp vref video bias comp fsa avdd avss pll_vco avss pvddreg dvdd18 dvss pvss ccir_clk pvdd65 gpio1_sscl gpio2_ssda pvdd33 gpio3_mscl gpio4_msda pclk_o gpio8 gpio9 gpio10 gpio11 pvss vd_v1 vd_v2 vd_v3 vd_v4 vd_vsg1 vd_vsg2 vd_vsub pvdd33 ccd_rg ccd_h1 ccd_h2 pvss afe_shp afe_shd gpio7 ccir_d7 ccir_d6 avdd op_inp op_out adc_in pvdd33 gpio6_ohs gpio5_pref pvss afe_ck afe_do gpoi0_csn rst_n xout ccir_d4 ccir_d5 xin avss
rev. 1.00 4 september 30, 2011 HT82V863R pin description pin description name dir typ pul ma ccir_d3 o 4 ccir656 encoder data output bit 3 ccir_d2 o 4 ccir656 encoder data output bit 2 ccir_d1 o 4 ccir656 encoder data output bit 1 ccir_d0 o 4 ccir656 encoder data output bit 0 pvss p pad ground pin afe_din9 i ccd data input bit 9 afe_din8 i ccd data input bit 8 afe_din7 i ccd data input bit 7 afe_din6 i ccd data input bit 6 pvdd33 p 3.3v pad power pin afe_din5 i ccd data input bit 5 afe_din4 i ccd data input bit 4 afe_din3 i ccd data input bit 3 afe_din2 i ccd data input bit 2 afe_din1 i ccd data input bit 1 afe_din0 i ccd data input bit 0 pvss p pad ground pin pvdd33 p 3.3v pad power pin afe_obp o 4 clamp pulse output for optical black function afe_pblk o 4 blanking pulse output for afe afe_adclp o 4 clamp pulse output for afe afe_shd o 4 sample hold pulse output for data afe_shp o 4 sample hold pulse output for reference pvss p pad ground pin ccd_h2 o 12 horizontal shift register clock 2 for ccd ccd_h1 o 12 horizontal shift register clock 1 for ccd ccd_rg o 12 reset pulse output for ccd pvdd33 p 3.3v pad power pin vd_vsub o 4 ccd substrate bias pulse output for vertical driver vd_vsg2 o 4 readout pulse 2 for vertical driver vd_vsg1 o 4 readout pulse 1 for vertical driver vd_v4 o 4 vertical shift register clock 4 for vertical driver vd_v3 o 4 vertical shift register clock 3 for vertical driver vd_v2 o 4 vertical shift register clock 2 for vertical driver vd_v1 o 4 vertical shift register clock 1 for vertical driver pvss p pad ground pin pclk_o o 12 pixel clock output gpio8 b u 4 gpio [8] or pwm [3] output gpio9 b u 4 gpio [9] or uart receiver data input, rxd. gpio10 b u 4 gpio [10] gpio11 b u 4 gpio [11] gpio4_msda b u 4 gpio [4] or master mode i 2 c data input/output gpio3_mscl b u 4 gpio [3] or master mode i 2 c clock output pvdd33 p 3.3v pad power pin gpio2_ssda b u 4 gpio [2] or slave mode i 2 c data input/output gpio1_sscl b u 4 gpio [1] or slaver mode i 2 c clock input
rev. 1.00 5 september 30, 2011 HT82V863R pin description name dir typ pul ma pvdd65 p 6.5v pad power pin pvss p pad ground pin ccir_clk o 12 ccir656 encoder clock output dvss p digital ground pin dvdd18 p 1.8v digital power pin pvddreg p 3.3v regulator power pin avss p op, dac and regulator ground pin. pll_vco ao pll vco output avss p op, dac and regulator ground pin avdd p 3.3v op and dac power pin fsa ao dac full-scale adjust control comp ao dac compensation pin bias ao dac current source bias pin vref ai dac bandgap reference voltage output video ao dac video output avdd p 3.3v op and dac power pin avss p op and dac ground pin op_inp ai op buffer positive input op_out ao op buffer output adc_in ai a/d converter analog input gpio7 b u gpio [7] or 27mhz clock input ccir_d7 o 4 ccir656 encoder data output bit 7 ccir_d6 o 4 ccir656 encoder data output bit 6 pvdd33 p 3.3v pad power pin gpio6_ohs b u 4 gpio [6] or pwm [2] output or uart transmitter data output, txd, or digital video hsync output. gpio5_pref b u 4 gpio [5] or pwm [1] output or power line reference clock input pvss p pad ground pin afe_ck o 4 spi clock output for afe afe_do o 4 spi data output for afe gpio0_csn b u 4 gpio[0] or pwm[0] output or uart transmitter data output, txd, or spi chip enable output for afe rst_n i s system reset, active low ccir_d5 o 4 ccir656 encoder data output bit 5 ccir_d4 o 4 ccir656 encoder data output bit 4 xout o oscillator output xin i oscillator input for mclk note: dir: pin direction, b: bi-directional, o: output, i: input ai: analog input, ao: analog output, typ: pin type t: tri-state, od: open-drain, s: schmitt trigger, p: power pin pul: pin internal pull up/down 75 resistor u: pull-up, d: pull-down, ma: pin driving current capability
rev. 1.00 6 september 30, 2011 HT82V863R note: these are stress ratings only . stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those l isted i n t he sp ecifcation i s n ot i mplied a nd p rolonged e xposure t o e xtreme c onditions m ay a ffect device reliability. recommended operating conditions symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 v cc v t op operating temperature -20 25 70 c f ck input clock frequency 28.7 mhz d.c. characteristics symbol parameter condition min. typ. max. unit v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i dd operating current 80 ma v t? schmitt trigger input low voltage 0.8 1.1 v v t+ schmitt trigger input high voltage 1.6 2.0 v r i input pull-up/pull-down resistance v il =0v or v ih =vcc 75 a.c. characteristics clock characteristics symbol parameter min. typ. max. unit t ck oscillator clock frequency -500ppm 28.7 +500ppm mhz d ck oscillator clock duty cycle 45 50 55 % reset characteristics symbol parameter min. typ. max. unit t rst_n external system reset pulse width 1 ms absolute maximum ratings power supply v oltage v cc ........................ -0.3v~4.3v input v oltage v in ............................... -0.3v~v cc +0.3v output v oltage v out ............................ -0.3v~v cc +0.3v storage t emperature t stg ...................... -40c~150c
rev. 1.00 7 september 30, 2011 HT82V863R ccd input interface timing symbol parameter test condition min. typ. max. unit v dd conditions f s conversion frequency 3.0v 0.5 20 mhz t cyc clock cycle time 3.0v 50 ns t r clock rising time 3.0v 2 ns t f clock falling time 3.0v 2 ns t l clock low period 3.0v 23 ns t h clock high period 3.0v 23 ns t wr shr pulse width 3.0v 11 ns t wd shd pulse widh 3.0v 11 ns t dr shr sampling aperture 3.0v 4 ns t dd shd sampling aperture 3.0v 4 ns t psup data pulse setup 3.0v 2 ns t hold data pulse hold 3.0v 5 ns t sp sampling pulse non-overlay 3.0v 1 ns t supe enable pulse setup 3.0v 10 ns t holde enable pulse hold 3.0v 10 ns t supoc outck setup 3.0v 0 ns t holdc outck hold 3.0v 10 ns t dld 3-state disable delay 3.0v activehigh-z 20 ns t dle 3-state disable delay 3.0v high-zactive 20 ns t ol adc output data delay 3.0v 18 ns

note: normally, the afe asic registers are set to ignore outck, and only use adck.
rev. 1.00 8 september 30, 2011 HT82V863R tv encoder output interface timing ntsc vertical timing equalizing pulse and sync pulse interval timing table equalizing pulse and sync pulse interval timing. symbol characteristics( s) ntsc pal p duration of equalizing pulse 2.30.1 2.350.1 q 'xudwlrqrihogvqfkurql]lqjsxovh 27.1 27.3 r ,qwhuydoehwhhqhogvqfkurql]lqjsxovh 4.70.1 4.70.2 s build-up timing (10 to 90%) 0.20.1
rev. 1.00 9 september 30, 2011 HT82V863R details of line synchronizing signal table details of line synchronizing signal. symbol characteristics ( s) ntsc pal d synchronizing pulse 4.70.1 4.70.2 e build-up time of the line-blanking pulse 0.30.1 f build-up time of the line-synchronizing pulse 0.20.1 b line-blanking interval 9.2~10.3 120.2 c front porch 1.27~2.22 1.50.3 g start of sub-carrier burst 4.71~5.71 5.60.1 h duration of sub-carrier burst 2.23~3.11(91 cycles) 2.250.23(101 cycles) h nominal line period 63.5555 64 ccir656 encoder interface timing the ccir656 encoder connects to the digital component video signals using 525 lines for ntsc systems or 625 lines for pal systems. the data stream is a sequence of 8-bit bytes, transmitted at a rate of 27 mbbyte/s. the video pixel data horizontal scan lines are delimited in the stream using 4-byte long sa v (start of active v ideo) and ea v (end of active video) code sequences. individual pixels in a line are coded in ycbcr 4:2:2 format. after an sa v code (4 bytes) is sent, the frst 8 bits of cb (chroma u) data are sent and then 8-bit data of y (luma), followed by 8-bit data of cr (chroma v) for the next pixel and then 8 bits of y . tv system pal ( 625 lines) ntsc (525 lines) gllwdohogeodqnlq field 1 start (v=1) line 624 line 1 finish (v=0) line 23 line 10 field 2 start (v=1) line 311 line 264 finish (v=0) line 336 line 273 )gljlwdohoglghqwlfdwlrq field 1 f=0 line 1 line 4 field 2 f=1 line 313 line 266 video datfield-blanking defnition
rev. 1.00 10 september 30, 2011 HT82V863R horizontal timing one scan line parallel interface data spi interface timing symbol parameter conditions min. max. units f sk sk clock frequency 0 250 khz f skh sk high time 1 s f skl sk low time 1 s t cs minimum cs low time 1 s t css cs setup time 0.2 s t dh do hold time 70 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs=v il 0.4 s t wp write cycle time 15 ms
rev. 1.00 11 september 30, 2011 HT82V863R i 2 c interface timing

byte write timing page write timing
current read timing
random read timing
sequential read timing
rev. 1.00 12 september 30, 2011 HT82V863R

symbol parameter remark standard mode* v cc =5v10% unit min. max. min. max. f sk clock frequency 100 400 khz t high clock high time 4000 600 ns t low clock low time 4700 1200 ns t r sda and scl rise time note 1000 300 ns t f sda and scl fall time note 300 300 ns t hd:sta start condition hold time after this period the frst clock pulse is generated 4000 600 ns t su:sta start condition setup time only relevant for repeated start condition 4000 600 ns t hd:dat data iuput hold time 0 0 ns t su:dat data iuput setup time 200 100 ns t su:sto stop condition setup time 4000 600 ns t aa output valid from clock 3500 900 ns t buf bus free time time in which the bus must be free before a new transmission can start 4700 1200 ns t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns t wr write cycle time 5 5 ms a/d converter interface timing
rev. 1.00 13 september 30, 2011 HT82V863R functional description ccd interface the ccd interface is used to capture the image and re ceive t he cmyg cf a ccd ra w da ta a nd t he control si gnals g enerated f rom t he a nalog f ront-end module. then the ccd raw data together with the control signals will be correctly manipulated such as for bla ck cl amp operati on, bad pixel com pensation, etc. t he proc essed ra w da ta a nd c ontrol si gnals wi ll be eventually sent to the colour image processor to perform further image signal manipulations. colour image processor the heart of the survei llance ca mera is the colour image p rocessor in w hich the raw data derived from the ccd interface is processed. in addition to the colour mosaic interpolation, several colour image processor main functions include the edge extraction and e nhancement, c olour c orrection, a uto e xposure support and white balance, colour space transform, gamma correction and false colour suppression. timing generator this i s a program mable 96-ste p pre cision t iming generator e mbedded wi th a dl l t o pe rform t iming fne tuning and to generate all the ccd data related control timings. tv encoder this provides a 10-bit ycbcr digital input interface to accept the data stream sent from the colour image processor (or equivalent circuitry) and to convert the data i nto t he nt sc or p al t v c omposite signa l or y/c signal. line lock a line-lock function is available on most cctv cameras and is used to prevent picture colour rolling on the monitor , which results from the dif ference between t he su rveillance c amera e xposure fre quency and the ac power line frequency . colour rolling will cause a vital picture information loss and will be irritating for the viewer. a/d converter the device provides a 6-bit a/d converter. osd generator the device can generate up to 4 lines with a maximum of 16 c haracters, e ach of whi ch c an be up t o 16 16 font size. the scaling factor can be up to 8 times on both the horizontal direction and vertical direction. back light compensation C blc the ba ck l ight com pensation wi ll provi de pe rfect exposure for an object in front of very strong back light, n o m atter whe ther t he m ain ob ject i s m oving toward the center , upper , lower , left, right part or any location in the screen. the HT82V863R device provides a smart adaptive blc algorithm to perform compensation, follow ed by the exposure level, w ith a fast speed so that no matter where on the screen the main object is moving to, it always provides a clear picture. dwdr digital wdr is a proprietary algorithm to provide clear i mages eve n unde r bac k l ight ci rcumstances where there are both very bright and very dark areas simultaneously i n t he vi ew of t he c amera. in short , dwdr allows the viewer to see details in both areas. ccir656 encoder the ccir656 e ncoder a ccepts t he da ta st ream derived from the colour image processor and converts the data into itu _r bt656 digital output signals. i 2 c interface the de vice i ntegrates a n ot p rom fo r fi rmware storage. the frmware can be easily programmed into the ot p rom usi ng t he in-syst em progra mming function and the i 2 c interface. programming considerations all configurations in this device are displayed in a user int erface window as part of the relevant development tool system. therefore, the detailed confguration and defnitions are not mentioned in this document. re fer t o t he c orresponding use rs m anual for more detailed confguration information.
rev. 1.00 14 september 30, 2011 HT82V863R system application diagram 1 ???? ? ???? ?????? ? ?????? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???? ?? ? ??
rev. 1.00 15 september 30, 2011 HT82V863R package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 64-pin lqfp (7mm7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.016 D f 0.005 D 0.009 g 0.053 D 0.057 h D D 0.063 i 0.002 D 0.006 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.13 D 0.23 g 1.35 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.20 0 D 7
rev. 1.00 16 september 30, 2011 HT82V863R 80-pin lqfp (10mm10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 D 0.476 b 0.390 D 0.398 c 0.469 D 0.476 d 0.390 D 0.398 e D 0.016 D f D 0.006 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 11.90 D 12.10 b 9.90 D 10.10 c 11.90 D 12.10 d 9.90 D 10.10 e D 0.40 D f D 0.16 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7
rev. 1.00 17 september 30, 2011 HT82V863R holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

▲Up To Search▲

Price & Availability of HT82V863R

	To Download HT82V863R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .